One of the problems which arises is the complexity and the power consumption of the very numerous interconnections between circuit elements.
A second problem, related to the complexity and to the variations in advanced technologies, is the great difficulty of obtaining synchronous operation (that is to say using one and the same clock domain) in a complete circuit and/or in a stack of circuits. This difficulty has prompted teams to propose architectures either of “Globally Asynchronous, Locally Synchronous” (GALS) type, in which the long-range communications are performed in an asynchronous manner, or that are totally asynchronous (the data senders and receivers manage between themselves the transmission of data without a central facility determining the instants of exchanges for all).
For the sender, the asynchronous communication consists in sending a data item only if it has received beforehand an acknowledgment signal on the part of the receiver, showing that the receiver has already recorded a previous data item and is available to receive another one.
Typically, a robust asynchronous communication, of the type that is quasi-insensitive to lags, intended to transmit binary information bits 0 and 1, uses three conductors. A first conductor is reserved for the transmission of the “0”s: it transmits a pulse when it has to dispatch a 0 and then reverts to its quiescent level where it remains until it has to transmit a 0 again. A second conductor is reserved for the transmission of the “1”s; it transmits a pulse when it has to dispatch a 1 and it reverts to its quiescent level until it has to transmit a 1 again. Finally, a third conductor is intended to transmit an acknowledgment signal from the receiver to the sender. This acknowledgment signal is a pulse dispatched when the receiver has recorded a data item; the sender uses this signal to return the conductor which transmitted the data item to its quiescent level. A drawback of asynchronous communications is therefore the use of a larger number of conductors than for synchronous communications. This point is particularly sensitive in the case of a stack of chips, interconnected vertically by through vias, the latter occupying a significant area of silicon.
To reduce the number of conductors, it has already been proposed to work in ternary mode and to transmit the 1s and also the 0s on a single conductor. The conductor is at an intermediate quiescent potential level Vmed as long as it is not transmitting a data item. The sender causes this potential to switch to a higher level Vhigh to transmit a 1, or to a lower level Vlow to transmit a 0. The receiver detects a change of level, determines the data item as a function of the direction of the change, and dispatches an acknowledgment signal on the conductor reserved for this use.